74HC191PW集成电路(IC)计数器除法器规格书PDF中文资料
厂商型号 |
74HC191PW |
参数属性 | 74HC191PW 封装/外壳为16-TSSOP(0.173",4.40mm 宽);包装为管件;类别为集成电路(IC) > 计数器,除法器;产品描述:IC 4BIT BINARY UP/DN CNT 16TSSOP |
功能描述 | Presettable synchronous 4-bit binary up/down counter |
文件大小 |
296.75 Kbytes |
页面数量 |
18 页 |
生产厂商 | Nexperia B.V. All rights reserved |
企业简称 |
NEXPERIA【安世】 |
中文名称 | 安世半导体(中国)有限公司官网 |
原厂标识 | |
数据手册 | |
更新时间 | 2024-6-5 18:10:00 |
74HC191PW规格书详情
1. General description
The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains four
master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and
synchronous count-up and count-down operation. Asynchronous parallel load capability permits
the counter to be preset to any desired value. Information present on the parallel data inputs (D0
to D3) is loaded into the counter and appears on the outputs when the parallel load (PL) input is
LOW. This operation overrides the counting function. Counting is inhibited by a HIGH level on the
count enable (CE) input. When CE is LOW internal state changes are initiated synchronously by
the LOW-to-HIGH transition of the clock input. The up/down (U/D) input signal determines the
direction of counting as indicated in the function table. The CE input may go LOW when the clock is
in either state, however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH.
Also, the U/D input should be changed only when either CE or CP is HIGH. Overflow/underflow
indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC).
The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down
mode or reaches '15' in the count-up-mode. The TC output will remain HIGH until a state change
occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a
clock signal because it is subject to decoding spikes. The TC signal is used internally to enable
the RC output. When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP). This
feature simplifies the design of multistage counters as shown in Fig. 5 and Fig. 6. In Fig. 5, each
RC output is used as the clock input to the next higher stage. It is only necessary to inhibit the
first stage to prevent counting in all stages, since a HIGH on CE inhibits the RC output pulse. The
timing skew between state changes in the first and last stages is represented by the cumulative
delay of the clock as it ripples through the preceding stages. This can be a disadvantage of this
configuration in some applications. Fig. 6 shows a method of causing state changes to occur
simultaneously in all stages. The RC outputs propagate the carry/borrow signals in ripple fashion
and all clock inputs are driven in parallel. In this configuration the duration of the clock LOW state
must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through
to the last stage before the clock goes HIGH. Since the RC output of any package goes HIGH
shortly after its CP input goes HIGH there is no such restriction on the HIGH-state duration of the
clock. In Fig. 7, the configuration shown avoids ripple delays and their associated restrictions.
Combining the TC signals from all the preceding stages forms the CE input for a given stage. An
enable must be included in each carry gate in order to inhibit counting. The TC output of a given
stage it not affected by its own CE signal therefore the simple inhibit scheme of Fig. 5 and Fig. 6
does not apply. Inputs include clamp diodes. This enables the use of current limiting resistors to
interface inputs to voltages in excess of VCC.
2. Features and benefits
• Wide supply voltage range from 2.0 to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• CMOS input levels
• Synchronous reversible counting
• Asynchronous parallel load
• Count enable control for synchronous expansion
• Single up/down control input
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
74HC191PW属于集成电路(IC) > 计数器,除法器。安世半导体(中国)有限公司制造生产的74HC191PW计数器,除法器计数器和除法器 IC 是数字逻辑器件,可对输入发生的逻辑转换进行计数,然后使用多个并行输出重新发送累加的计数,和/或生成单个输出信号转换,从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数,它们还可用于各种频率合成应用。
产品属性
- 产品编号:
74HC191PW,118
- 制造商:
Nexperia USA Inc.
- 类别:
集成电路(IC) > 计数器,除法器
- 系列:
74HC
- 包装:
管件
- 逻辑类型:
二进制计数器
- 方向:
上,下
- 定时:
同步
- 触发器类型:
正边沿
- 工作温度:
-40°C ~ 125°C
- 安装类型:
表面贴装型
- 封装/外壳:
16-TSSOP(0.173",4.40mm 宽)
- 供应商器件封装:
16-TSSOP
- 描述:
IC 4BIT BINARY UP/DN CNT 16TSSOP
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
NXP/恩智浦 |
1926+ |
sop16 |
6852 |
只做原装正品现货!或订货假一赔十! |
询价 | ||
Nexperia(安世) |
1923+ |
TSSOP-16 |
2260 |
向鸿只做原装正品,我们没有假货!仓库库存优势 |
询价 | ||
NEXPERIA/安世 |
2023+ |
TSSOP-16 |
8635 |
一级代理优势现货,全新正品直营店 |
询价 | ||
NXP-恩智浦 |
24+25+/26+27+ |
逻辑计算IC |
36218 |
一一有问必回一特殊渠道一有长期订货一备货HK仓库 |
询价 | ||
NEXPERIA/安世 |
22+ |
SOT403-1 |
50000 |
原装正品.假一罚十 |
询价 | ||
NEXPERIA/安世 |
2122+ |
SOT403-1 |
10990 |
全新原装正品现货,假一赔十 |
询价 | ||
Nexperia |
23/22+ |
NA |
9000 |
代理渠道.实单必成 |
询价 | ||
NEXPERIA |
21+ |
TSSOP-16 |
56000 |
公司进口原装现货 批量特价支持 |
询价 | ||
Nexperia(安世) |
22+ |
NA |
500000 |
万三科技,秉承原装,购芯无忧 |
询价 | ||
NEXPERIA/安世 |
22+ |
SOT403-1 |
8900 |
英瑞芯只做原装正品!!! |
询价 |