Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

文件：44.7 Kbytes 页数：7 Pages

PHI

飞利浦

Dual 2-to-4 line decoder/demultiplexer

General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4

文件：156.99 Kbytes 页数：17 Pages

恩XP

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

文件：243.29 Kbytes 页数：13 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

文件：44.7 Kbytes 页数：7 Pages

PHI

飞利浦

Dual 2-to-4 line decoder/demultiplexer

General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4

文件：156.99 Kbytes 页数：17 Pages

恩XP

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input f

文件：242.51 Kbytes 页数：13 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual 2-to-4 line decoder/demultiplexer

文件：762.31 Kbytes 页数：18 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual 2-to-4 line decoder/demultiplexer

文件：762.31 Kbytes 页数：18 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual 2-to-4 line decoder/demultiplexer

The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. • Input levels:• For 74HC139: CMOS level\n• For 74HCT139: TTL level\n\n• Demultiplexing capability\n• 2 independent 2-to-4 decoders\n• Multifunction capability\n• Suitable for memory decoding, data routing or code conversion\n• Complies with JEDEC standard no. 7A\n• Active LOW mutually exclusive out;

Nexperia

安世

74HC CMOS logic IC series

Function：Dual 2-to-4 Line Decoder\nNumber of Circuits：2\nRoHS Compatible Product(s) (#)：Available\nAssembly bases：日本 Power Dissipation PD 500 mW ;

Toshiba

东芝