Octal Serial/Parallel Register with Sign Extend

General Description The ’F322 is an 8-bit shift register with provision for either serial or parallel loading and with TRI-STATEÉ parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the r

文件：178.28 Kbytes 页数：10 Pages

NSC

国半

8-bit serial/parallel register with sign extend 3-State

DESCRIPTION The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-State parallel outputs plus a bi-state serial output. Parallel data inputs and outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the c

文件：80.62 Kbytes 页数：9 Pages

PHI

飞利浦

8-bit serial/parallel register with sign extend 3-State

DESCRIPTION The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-State parallel outputs plus a bi-state serial output. Parallel data inputs and outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the c

文件：80.62 Kbytes 页数：9 Pages

PHI

飞利浦

8-bit serial/parallel register with sign extend 3-State

DESCRIPTION The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-State parallel outputs plus a bi-state serial output. Parallel data inputs and outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the c

文件：80.62 Kbytes 页数：9 Pages

PHI

飞利浦

Octal Serial/Parallel Register with Sign Extend

General Description The ’F322 is an 8-bit shift register with provision for either serial or parallel loading and with TRI-STATEÉ parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the r

文件：178.28 Kbytes 页数：10 Pages

NSC

国半

Octal Serial/Parallel Register with Sign Extend

General Description The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-STATE parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the ris

文件：53.91 Kbytes 页数：6 Pages

Fairchild

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