74AUP2G240GN中文资料Low-power dual inverting buffer/line driver; 3-state数据手册Nexperia规格书

描述 Description

The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE causes the output to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is HIGH.

特性 Features

• Wide supply voltage range from 0.8 V to 3.6 V
• Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V)
• JESD8-7 (1.2 V to 1.95 V)
• JESD8-B (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F Class 3A exceeds 5000 V
• CDM JESD22-C101E exceeds 1000 V
• Low static power consumption; ICC = 0.9 μA (maximum)
• Inputs accept voltages up to 3.6 V
• Input-disable feature allows floating input conditions
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C