23S09T-1DCG集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

FEATURES:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five and one bank of

four outputs

• Separate output enable for each output bank

• Output Skew < 250ps

• Low jitter <200 ps cycle-to-cycle

• No external RC network required

• Operates at 2.5V VDD

• Spread spectrum compatible

• Available in SOIC package