首页 >SN74F112DR>规格书列表
| 零件编号 | 下载&订购 | 功能描述 | 制造商&上传企业 | LOGO |
|---|---|---|---|---|
SN74F112DR | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP | TI1Texas Instruments(TI) 德州仪器德州仪器 (TI) | TI1 | |
SN74F112DR | 包装：管件 封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 16SOIC | TITexas Instruments 德州仪器美国德州仪器公司 | TI | |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP | TI1Texas Instruments(TI) 德州仪器德州仪器 (TI) | TI1 | ||
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP | TI1Texas Instruments(TI) 德州仪器德州仪器 (TI) | TI1 | ||
DualJKNegativeEdge-TriggeredFlip-Flop GeneralDescription The74F112containstwoindependent,high-speedJKflipflopswithDirectSetandClearinputs.Synchronousstatechangesareinitiatedbythefallingedgeoftheclock.Triggeringoccursatavoltageleveloftheclockandisnotdirectlyrelatedtothetransitiontime.TheJ | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | Fairchild | ||
DualJKNegativeEdge-TriggeredFlip-Flop | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | Fairchild | ||
DualJ-Knegativeedge-triggeredflip-flop DESCRIPTION The74F112,DualNegativeEdge-TriggeredJK-TypeFlip-Flop,featureindividualJ,K,Clock(CPn),Set(SD)andReset(RD)inputs,true(Qn)andcomplementary(Qn)outputs. TheSDandRDinputs,whenLow,setorresettheoutputsasshownintheFunctionTable,regardlessofthelevel | PhilipsROYAL PHILIPS 飞利浦荷兰皇家飞利浦 | Philips | ||
DualJKNegativeEdge-TriggeredFlip-Flop | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | Fairchild | ||
DualJKNegativeEdge-TriggeredFlip-Flop GeneralDescription The74F112containstwoindependent,high-speedJKflipflopswithDirectSetandClearinputs.Synchronousstatechangesareinitiatedbythefallingedgeoftheclock.Triggeringoccursatavoltageleveloftheclockandisnotdirectlyrelatedtothetransitiontime.TheJ | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | Fairchild | ||
DualJKNegativeEdge-TriggeredFlip-Flop | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | Fairchild | ||
DualJKNegativeEdge-TriggeredFlip-Flop GeneralDescription The74F112containstwoindependent,high-speedJKflipflopswithDirectSetandClearinputs.Synchronousstatechangesareinitiatedbythefallingedgeoftheclock.Triggeringoccursatavoltageleveloftheclockandisnotdirectlyrelatedtothetransitiontime.TheJ | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | Fairchild | ||
DualJKNegativeEdge-TriggeredFlip-Flop GeneralDescription The74F112containstwoindependent,high-speedJKflipflopswithDirectSetandClearinputs.Synchronousstatechangesareinitiatedbythefallingedgeoftheclock.Triggeringoccursatavoltageleveloftheclockandisnotdirectlyrelatedtothetransitiontime.TheJ | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | Fairchild | ||
DualJKNegativeEdge-TriggeredFlip-Flop | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | Fairchild | ||
DualJ-Knegativeedge-triggeredflip-flop DESCRIPTION The74F112,DualNegativeEdge-TriggeredJK-TypeFlip-Flop,featureindividualJ,K,Clock(CPn),Set(SD)andReset(RD)inputs,true(Qn)andcomplementary(Qn)outputs. TheSDandRDinputs,whenLow,setorresettheoutputsasshownintheFunctionTable,regardlessofthelevel | PhilipsROYAL PHILIPS 飞利浦荷兰皇家飞利浦 | Philips | ||
DualJ-Knegativeedge-triggeredflip-flop DESCRIPTION The74F112,DualNegativeEdge-TriggeredJK-TypeFlip-Flop,featureindividualJ,K,Clock(CPn),Set(SD)andReset(RD)inputs,true(Qn)andcomplementary(Qn)outputs. TheSDandRDinputs,whenLow,setorresettheoutputsasshownintheFunctionTable,regardlessofthelevel | PhilipsROYAL PHILIPS 飞利浦荷兰皇家飞利浦 | Philips | ||
DUALJKNEGATIVEEDGE-TRIGGEREDFLIP-FLOP TheMC74F112containstwoindependent,high-speedJKflip-flopswithDirectSetandClearinputs.Synchronousstatechangesareinitiatedbythefallingedgeoftheclock.Triggeringoccursatavoltageleveloftheclockandisnotdirectlyrelatedtothetransitiontime.TheJandKinputscanc | MotorolaMotorola, Inc 摩托罗拉 | Motorola | ||
DUALJKNEGATIVEEDGE-TRIGGEREDFLIP-FLOP TheMC74F112containstwoindependent,high-speedJKflip-flopswithDirectSetandClearinputs.Synchronousstatechangesareinitiatedbythefallingedgeoftheclock.Triggeringoccursatavoltageleveloftheclockandisnotdirectlyrelatedtothetransitiontime.TheJandKinputscanc | MotorolaMotorola, Inc 摩托罗拉 | Motorola | ||
DUALJKNEGATIVEEDGE-TRIGGEREDFLIP-FLOP TheMC74F112containstwoindependent,high-speedJKflip-flopswithDirectSetandClearinputs.Synchronousstatechangesareinitiatedbythefallingedgeoftheclock.Triggeringoccursatavoltageleveloftheclockandisnotdirectlyrelatedtothetransitiontime.TheJandKinputscanc | MotorolaMotorola, Inc 摩托罗拉 | Motorola | ||
DUALJKNEGATIVEEDGE-TRIGGEREDFLIP-FLOP TheMC74F112containstwoindependent,high-speedJKflip-flopswithDirectSetandClearinputs.Synchronousstatechangesareinitiatedbythefallingedgeoftheclock.Triggeringoccursatavoltageleveloftheclockandisnotdirectlyrelatedtothetransitiontime.TheJandKinputscanc | MotorolaMotorola, Inc 摩托罗拉 | Motorola | ||
DualJ-Knegativeedge-triggeredflip-flop DESCRIPTION The74F112,DualNegativeEdge-TriggeredJK-TypeFlip-Flop,featureindividualJ,K,Clock(CPn),Set(SD)andReset(RD)inputs,true(Qn)andcomplementary(Qn)outputs. TheSDandRDinputs,whenLow,setorresettheoutputsasshownintheFunctionTable,regardlessofthelevel | PhilipsROYAL PHILIPS 飞利浦荷兰皇家飞利浦 | Philips |
产品属性
- 产品编号：
SN74F112DR
- 制造商：
Texas Instruments
- 类别：
集成电路（IC） > 触发器
- 系列：
74F
- 包装：
管件
- 功能：
设置（预设）和复位
- 类型：
JK 型
- 输出类型：
补充型
- 不同 V、最大 CL 时最大传播延迟：
6.5ns @ 5V，50pF
- 触发器类型：
负边沿
- 电流 - 输出高、低：
1mA，20mA
- 电压 - 供电：
4.5V ~ 5.5V
- 工作温度：
0°C ~ 70°C（TA）
- 安装类型：
表面贴装型
- 供应商器件封装：
16-SOIC
- 封装/外壳：
16-SOIC（0.154"，3.90mm 宽）
- 描述：
IC FF JK TYPE DUAL 1BIT 16SOIC
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Texas Instruments |
24+ |
SOIC-16 |
40491 |
TI优势主营型号-原装正品 |
询价 | ||
TI |
21+ |
SOP16 |
3200 |
全新原装,支持实单,非诚勿扰 |
询价 | ||
TI(德州仪器) |
23+ |
SOP16 |
2669 |
只做原装,提供一站式配单服务,代工代料。BOM配单 |
询价 | ||
TI |
2020+ |
SOP16 |
2500 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
询价 | ||
TEXASINSTRU |
16+ |
原封装 |
482 |
原装现货假一罚十 |
询价 | ||
TI |
16+ |
NA |
8800 |
原装现货,货真价优 |
询价 | ||
TI |
SOP3.9mm |
16502 |
询价 | ||||
TI |
2000 |
2500 |
原装正品长期供货，如假包赔包换 徐小姐13714450367 |
询价 | |||
TMS |
06+ |
SOIC |
1000 |
自己公司全新库存绝对有货 |
询价 | ||
TI |
2020+ |
原厂封装 |
350000 |
100%进口原装正品公司现货库存 |
询价 |
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