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RM7000-200S规格书详情
Description
PMC-Sierra’s RM7000 is a highly integrated symmetric superscalar microprocessor capable of issuing two instructions each processor cycle. It has two high-performance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating point unit. To keep its multiple execution units running efficiently, the RM7000 integrates not only 16 KB 4-way set associative instruction and data caches but backs them up with an integrated 256 KB 4-way set associative secondary as well. For maximum efficiency, the data and secondary caches are write-back and non-blocking. An optional external tertiary cache provides high-performance capability even in applications having very large data sets.
A RM5200 Family compatible, operating system friendlymemory management unit with a 64/48-entry fully associative TLB and a high-performance 64-bit system interface supporting multiple outstanding reads with out-of-order return and hardware prioritized and vectored interrupts round out the main features of the processor.
The RM7000 is ideally suited for high-end embedded control applications such as internetworking, high-performance image manipulation, high-speed printing, and 3-D visualization. The RM7000 is also applicable to the low end workstation market where its balanced integer and floating-point performance and direct support for a large tertiary cache (up to 8 MB) provide outstanding price/performance.
Features
• Dual Issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance
• 200, 250, 266, 300 MHz operating frequency
• >500 Dhrystone 2.1 MIPS @ 300 MHz
• High-performance system interface
• 1000 MB per second peak throughput
• 125 MHz max. freq., multiplexed address/data
• Supports two outstanding reads with out-of-order return
• Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
• Integrated primary and secondary caches — all are 4-way set associative with 32 byte line size
• 16 KB instruction, 16 KB data, 256 KB on-chip secondary
• Per line cache locking in primaries and secondary
• Fast Packet Cache™ increases system efficiency in networking applications
• Integrated external cache controller (up to 8 MB)
• High-performance floating-point unit — 600 MFLOPS maximum
• Single cycle repeat rate for common single-precision operations and some double-precision operations
• Single cycle repeat rate for single-precision combined multiply-add operations
• Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations
• MIPS IV Superset Instruction Set Architecture
• Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution
• Single-cycle floating-point multiply-add
• Integrated memory management unit
• Fully associative joint TLB (shared by I and D translations)
• 64/48 dual entries map 128/96 pages
• Variable page size
• Embedded application enhancements
• Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and three operand multiply instruction (MUL)
• I&D Test/Break-point (Watch) registers for emulation & debug
• Performance counter for system and software tuning & debug
• Fourteen fully prioritized vectored interrupts - 10 external, 2 internal, 2 software
• Fully static CMOS design with dynamic power down logic
• RM5271 pin compatible, 304 pin TBGA package, 31x31 mm
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
PMC |
20+ |
BGA |
67500 |
原装优势主营型号-可开原型号增税票 |
询价 | ||
PMC |
1948+ |
BGA |
6852 |
只做原装正品现货!或订货假一赔十! |
询价 | ||
PMC |
22+ |
BGA |
2978 |
100%全新原装公司现货供应!随时可发货 |
询价 | ||
QED |
2023+ |
BGA |
80000 |
一级代理/分销渠道价格优势 十年芯程一路只做原装正品 |
询价 | ||
PMC |
23+ |
BGA |
26 |
原装正品现货 |
询价 | ||
PMC |
22+ |
BGA |
6868 |
原装现货,可开13%税票 |
询价 | ||
PMC |
23+ |
BGA |
9800 |
全新原装现货,假一赔十 |
询价 | ||
PMC |
23+ |
BGA |
5700 |
绝对全新原装!现货!特价!请放心订购! |
询价 | ||
PMC |
21+ |
BGA |
35200 |
一级代理/放心采购 |
询价 | ||
PMC |
22+ |
BGA |
2000 |
原装正品现货 |
询价 |