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RM5231-200-Q中文资料PDF规格书

RM5231-200-Q
厂商型号

RM5231-200-Q

功能描述

RM5231??Microprocessor with 32-Bit System Bus Data Sheet Released

文件大小

630.34 Kbytes

页面数量

39

生产厂商 PMC-Sierra
企业简称

PMC

中文名称

PMC-Sierra官网

原厂标识
数据手册

下载地址一下载地址二

更新时间

2024-6-18 22:50:00

RM5231-200-Q规格书详情

Hardware Overview

The RM5231 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the RM5231 are briefly described in this section.

Features

• Dual Issue superscalar microprocessor

• 150, 200, & 250 MHz operating frequencies

• 300 Dhrystone2.1 MIPS

• System interface optimized for embedded applications

• 32-bit system interface lowers total system cost

• High-performance write protocols maximize uncached write bandwidth

• Processor clock multipliers: 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9

• 2.5 V core with 3.3 V IOs

• IEEE 1149.1 JTAG boundary scan

• Integrated on-chip caches

• 32 KB instruction and 32 KB data — 2 way set associative

• Per set locking

• Virtually indexed, physically tagged

• Write-back and write-through on a per page basis

• Pipeline restart on first doubleword for data cache misses

• Integrated memory management unit

• Fully associative joint TLB (shared by I and D translations)

• 48 dual entries map 96 pages

• Variable page size (4 KB to 16 MB in 4x increments)

• High-performance floating-point unit — up to 500 MFLOPS

• Single cycle repeat rate for common single-precision operations and some double precision operations

• Two cycle repeat rate for double-precision multiply and double precision combined multiply-add operations

• Single cycle repeat rate for single-precision combined multiply-add operation

• MIPS IV instruction set

• Floating point multiply-add instruction increases performance in signal processing and graphics applications

• Conditional moves to reduce branch frequency

• Index address modes (register + register)

• Embedded application enhancements

• Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply instruction

• I and D cache locking by set

• Optional dedicated exception vector for interrupts

• Fully static 0.25 micron CMOS design with power down logic

• Standby reduced power mode with WAIT instruction

• 2.5 V core with 3.3 V I/O

• 128-pin Power-Quad 4 (QFP) package

供应商 型号 品牌 批号 封装 库存 备注 价格
QED
23+
QFP208
20000
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询价
QED
24+
NA
990000
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1736+
QFN
8298
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CORTINA
23+
QFP
8230
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QED
QFP208
00+
40
全新原装进口自己库存优势
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QED
2339+
QFP
5825
公司原厂原装现货假一罚十!特价出售!强势库存!
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QED
2138+
QFP
8960
专营BGA,QFP原装现货,假一赔十
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PMC
QFP
68500
一级代理 原装正品假一罚十价格优势长期供货
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QED
QFP
699839
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PMC
24+
QFP
6868
原装现货,可开13%税票
询价