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QL2009-1PF144I中文资料PDF规格书
QL2009-1PF144I规格书详情
[QuickLogic]
PRODUCT SUMMARY
The QL2009 is a 9,000 usable ASIC gate,16,000 usable PLD gate member of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics.
FEATURES
Ultimate Verilog/VHDL Silicon Solution
- Abundant, high-speed interconnect eliminates manual routing
- Flexible logic cell provides high efficiency and performance
- Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
- 16-bit counter speeds exceeding 200 MHz
- 9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os
- 3-layer metal ViaLink process for small die sizes
- 100 routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
- Complex functions (up to 16 inputs) in a single logic cell
- High synthesis gate utilization from logic cell fragments
- Full IEEE Standard JTAG boundary scan capability
- Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
- 3.3V and 5.0V operation with low standby power
- I/O pin-compatibility between different devices in the same packages
- PCI compliant (at 5.0V), full speed 33 MHz implementations
- High design security provided by security fuses
Total of 225 I/O Pins
- 217 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
Four Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and reset - each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O register clock, reset, enable; and output enable controls - each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output delays under 6 ns
- Datapath speeds exceeding 225 MHz
- Counter speeds over 200 MHz
产品属性
- 型号:
QL2009-1PF144I
- 功能描述:
3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
QUICKLOGIC |
22+ |
QFP208 |
354000 |
询价 | |||
QUALCOMM |
23+ |
QFP |
1002 |
全新原装现货 |
询价 | ||
QUICKOGIC |
23+ |
SOP8 |
5000 |
原装正品,假一罚十 |
询价 | ||
QUICKLOGIC |
2023+ |
80000 |
一级代理/分销渠道价格优势 十年芯程一路只做原装正品 |
询价 | |||
QUALCOMM |
23+ |
QFP |
8230 |
全新原装真实库存含13点增值税票! |
询价 | ||
QUICKLOGTC |
589220 |
16余年资质 绝对原盒原盘 更多数量 |
询价 | ||||
QUICKLOGIC |
23+ |
QFP-208 |
4500 |
全新原装、诚信经营、公司现货销售 |
询价 | ||
QC |
23+ |
65480 |
询价 | ||||
QUALCOMM |
2138+ |
QFP |
8960 |
专营BGA,QFP原装现货,假一赔十 |
询价 | ||
QUICKLOGI |
21+ |
QFP208 |
35400 |
全新原装现货/假一罚百! |
询价 |