DESCRIPTION

The S/UNI-ATLAS-1K800 is a bi-directional ATM Layer device that implements the ATM layer functions including header translation, policing, fault management, performance monitoring, per-connection and per-PHY counting. The S/UNIATLAS-1K800 is intended to be situated between a switch core and a physical layer device. The S/UNI-ATLAS-1K800 supports a sustained throughput of 1.42x106 cells/s in both the ingress (from the PHY into the switch core) and the egress (from the switch core to the PHY device) directions. The S/UNI-ATLAS-1K800 uses external synchronous flow-through SRAM to store the perconnection data structures. The device is capable of supporting up to 1024 connections.

FEATURES

• Monolithic single chip device which handles bi-directional ATM Layer functions including VPI/VCI address translation, cell appending (ingress only), cell rate policing (ingress only), per-connection counting and I.610 compliant OAM requirements for 1024 VCs (virtual connections).

• Instantaneous bi-directional transfer rate of 800 Mbit/s supports a bidirectional cell transfer rate of 1.42x106 cells/s (one STS-12c or four STS-3c).

• The Ingress input interface supports an 8 or 16 bit SCI-PHY interface using direct addressing for up to 4 PHY devices (compatible with Utopia Level 1 cell-level handshaking) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2 compatible).

• The Ingress output interface supports an 8 or 16 bit SCI-PHY (52 – 64 byte extended ATM cell with prepend/postpend) interface (compatible with Utopia Level 1 cell-level handshaking) to a switch fabric.

• The Egress input interface supports an 8 or 16 bit extended cell format SCIPHY interface using direct addressing for up to 4 PHY devices (compatible with Utopia Level 1 cell-level handshaking) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2 compatible).

• The Egress output interface supports an 8 or 16 bit extended cell format SCIPHY interface using direct addressing for up to 4 PHY devices (compatible with Utopia Level 1 cell-level handshaking) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2 compatible).

• Compatible with a wide range of switching fabrics and traffic management architectures including per-VC or per-PHY queuing.

• Highly flexible OAM-type cell and connection identification which can use arbitrary PHYID/VPI/VCI values and/or cell appended bytes for connection identification (N.B. this is an ingress function only). A direct lookup function is provided in the egress direction. The direct lookup can use an arbitrary header or prepend/postpend location.

• Ingress functionality includes a highly flexible search engine that covers the entire PHYID/VPI/VCI address range, programmable dual leaky bucket UPC/NPC, per-connection CLP0 and CLP1 cell counts (programmable), OAM-PM termination, generation and monitoring, and OAM-FM termination, generation and alarm generation (monitoring).

• Egress functionality includes programmable direct lookup function, OAM-PM termination, generation and monitoring, per-connection CLP0 and CLP1 cell counts (programmable) and OAM-FM termination, generation and alarm generation (monitoring). An egress per-PHY output buffering scheme resolves the head-of-line blocking issue.

• UPC/NPC function is a programmable dual leaky bucket policing device with a programmable action (tag, discard, or count only) for each bucket. A total of 3 programmable 16 bit non-compliant cell counts are provided. The noncompliant cell counts may be programmed to count, for example, dropped CLP0 cells, dropped CLP1 cells, and tagged CLP0 cells. The UPC/NPC function also has a continuously violating mode, where a programmable action is taken on all cells regardless of their compliance. AAL5 partial packet discard is also provided so that the remainder of an AAL5 packet can be tagged or discarded if a single cell in the packet is tagged or discarded as a result of violating policing.

• In addition to the per-connection dual leaky bucket, a single leaky bucket UPC/NPC function is provided on a per-PHY basis. A programmable action (tag, discard or count only) may be configured for each PHY policing device. Three programmable non-compliant cell counts are provided for each PHY. The non-compliant cell counts may be programmed to count, for example, dropped CLP0 cells, dropped CLP1 cells and tagged CLP0 cells. The perPHY policing parameters and non-compliant cell counts are maintained in an on-chip RAM that can be programmed and read via the 16-bit general purpose microprocessor interface.

• Guaranteed Frame Rate frame-based policing selectable on a per-connection basis.

APPLICATIONS

• Mini DSL Access Multiplexers (Mini-DSLAMs).

• Multiservice Access Multiplexers.

• 3rd generation wireless base stations and base station controllers.

• Subscriber Access terminal devices.

• APON Subscriber Access CLE.

• LMDS Subscriber Access CLE.

• Integrated Access Devices.