The MPC8641 processor family integrates either one or two

Power Architecture® e600 processor cores with system

logic required for networking, storage, wireless

infrastructure, and general-purpose embedded applications.

The MPC8641 integrates one e600 core while the

MPC8641D integrates two cores.

This section provides a high-level overview of the MPC8641

and MPC8641D features. When referring to the MPC8641

throughout the document, the functionality described applies

to both the MPC8641 and the MPC8641D. Any differences

specific to the MPC8641D are noted.

Figure 1 shows the major functional units within the

MPC8641 and MPC8641D. The major difference between

the MPC8641 and MPC8641D is that there are two cores on the MPC8641D.

Features

The following lists an overview of the MPC8641 key feature set:

• Major features of the e600 core are as follows:

— High-performance, 32-bit superscalar microprocessor that implements the PowerPC ISA

— Eleven independent execution units and three register files

– Branch processing unit (BPU)

– Four integer units (IUs) that share 32 GPRs for integer operands

– 64-bit floating-point unit (FPU)

– Four vector units and a 32-entry vector register file (VRs)

– Three-stage load/store unit (LSU)

— Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,

respectively, in a cycle.

— Rename buffers

— Dispatch unit

— Completion unit

— Two separate 32-Kbyte instruction and data level 1 (L1) caches

— Integrated 1-Mbyte, eight-way set-associative unified instruction and data level 2 (L2) cache

with ECC

— 36-bit real addressing

— Separate memory management units (MMUs) for instructions and data

— Multiprocessing support features

— Power and thermal management

— Performance monitor

— In-system testability and debugging features

— Reliability and serviceability

• MPX coherency module (MCM)

— Ten local address windows plus two default windows

— Optional low memory offset mode for core 1 to allow for address disambiguation

• Address translation and mapping units (ATMUs)

— Eight local access windows define mapping within local 36-bit address space

— Inbound and outbound ATMUs map to larger external address spaces

— Three inbound windows plus a configuration window on PCI Express

— Four inbound windows plus a default window on serial RapidIO

— Four outbound windows plus default translation for PCI Express

— Eight outbound windows plus default translation for serial RapidIO with segmentation and

sub-segmentation support

• DDR memory controllers

— Dual 64-bit memory controllers (72-bit with ECC)

— Support of up to a 300-MHz clock rate and a 600-MHz DDR2 SDRAM

— Support for DDR, DDR2 SDRAM

— Up to 16 Gbytes per memory controller

— Cache line and page interleaving between memory controllers.

• Serial RapidIO interface unit

— Supports RapidIO Interconnect Specification, Revision 1.2

— Both 1x and 4x LP-Serial link interfaces

— Transmission rates of 1.25-, 2.5-, and 3.125-Gbaud (data rates of 1.0-, 2.0-, and 2.5-Gbps) per

lane

— RapidIO–compliant message unit

— RapidIO atomic transactions to the memory controller

• PCI Express interface

— PCI Express 1.0a compatible

— Supports x1, x2, x4, and x8 link widths

— 2.5 Gbaud, 2.0 Gbps lane

• Four enhanced three-speed Ethernet controllers (eTSECs)

— Three-speed support (10/100/1000 Mbps)

— Four IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab-compatible controllers

— Support of the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI

— Support a full-duplex FIFO mode for high-efficiency ASIC connectivity

— TCP/IP off-load

— Header parsing

— Quality of service support

— VLAN insertion and deletion

— MAC address recognition

— Buffer descriptors are backward compatible with PowerQUICC II and PowerQUICC III

programming models

— RMON statistics support

— MII management interface for control and status

• Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts and 48 internal interrupts

— Eight global high resolution timers/counters that can generate interrupts

— Allows processors to interrupt each other with 32b messages

— Support for PCI-Express message-shared interrupts (MSIs)

• Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 133 MHz

— Eight chip selects support eight external slaves

• Integrated DMA controller

— Four-channel controller

— All channels accessible by both the local and the remote masters

— Supports transfers to or from any local memory or I/O port

— Ability to start and flow control each DMA channel from external 3-pin interface

• Device performance monitor

— Supports eight 32-bit counters that count the occurrence of selected events

— Ability to count up to 512 counter-specific events

— Supports 64 reference events that can be counted on any of the 8 counters

— Supports duration and quantity threshold counting

— Burstiness feature that permits counting of burst events with a programmable time between

bursts

— Triggering and chaining capability

— Ability to generate an interrupt on overflow

• Dual I2C controllers

— Two-wire interface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

• Boot sequencer

— Optionally loads configuration data from serial ROM at reset via the I2C interface

— Can be used to initialize configuration registers and/or memory

— Supports extended I2C addressing mode

— Data integrity checked with preamble signature and CRC

• DUART

— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

• IEEE 1149.1-compatible, JTAG boundary scan

• Available as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA)