The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

Features

• Ideal for Addressable Register Applications

• Clock Enable for Address and Data Synchronization Applications

• Eight Edge-Triggered D Flip-Flops

• Buffered Common Clock

• Outputs Source/Sink 24 mA

• See MC74AC273 for Master Reset Version

• See MC74AC373 for Transparent Latch Version

• See MC74AC374 for 3-State Version

• ACT377 Has TTL Compatible Inputs

• MSL = 1 for all Surface Mount

• Chip Complexity: 292 FETs or 73 Gates

• Pb−Free Packages are Available

MC74ACT377MEL属于集成电路（IC） > 触发器。安森美半导体公司制造生产的MC74ACT377MEL触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。