DESCRIPTION

ISSIs 128Mb Mobile Synchronous DRAM achieves highspeed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock input. Both write and read accesses to the SDRAM are burst oriented. The 128Mb Mobile Synchronous DRAM is designed to minimize current consumption making it ideal for low-power applications. Both TSOP and BGA packages are offered, including industrial grade products.

FEATURES

• Fully synchronous; all signals referenced to a positive clock edge

• Internal bank for hiding row access and precharge

• Programmable CAS latency: 2, 3

• Programmable Burst Length: 1, 2, 4, 8, and Full Page

• Programmable Burst Sequence:

• Sequential and Interleave

• Auto Refresh (CBR)

• TCSR (Temperature Compensated Self Refresh)

• PASR (Partial Arrays Self Refresh): 1/16, 1/8, 1/4, 1/2, and Full

• Deep Power Down Mode (DPD)

• Driver Strength Control (DS): 1/4, 1/2, and Full