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IDT72T2098L6BBI中文资料PDF规格书

IDT72T2098L6BBI
厂商型号

IDT72T2098L6BBI

功能描述

2.5 VOLT HIGH-SPEED TeraSync??DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION

文件大小

481.75 Kbytes

页面数量

51

生产厂商 Integrated Device Technology, Inc.
企业简称

IDT集成器

中文名称

深圳市集成器件技术有限公司官网

原厂标识
数据手册

下载地址一下载地址二

更新时间

2024-5-14 17:02:00

IDT72T2098L6BBI规格书详情

DESCRIPTION:

The IDT72T2098/72T20108/72T20118/72T20128 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with the ability to read and write data on both rising and falling edges of clock. The device has a flexible x20/x10 Bus-Matching mode and the option to select Single or Double Data clock rates for input and output ports.

FEATURES:

• Choose among the following memory organizations:

IDT72T2098 - 32,768 x 20/65,536 x 10

IDT72T20108 - 65,536 x 20/131,072 x 10

IDT72T20118 - 131,072 x 20/262,144 x 10

IDT72T20128 - 262,144 x 20/524,288 x 10

• Up to 250MHz Operation of Clocks

- 4ns read/write cycle time, 3.2ns access time

• Users selectable input port to output port data rates, 500Mb/s Data Rate

-DDR to DDR

-DDR to SDR

-SDR to DDR

-SDR to SDR

• User selectable HSTL or LVTTL I/Os

• Read Enable & Read Clock Echo outputs aid high speed operation

• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage

• 3.3V Input tolerant

• Mark & Retransmit, resets read pointer to user marked position

• Write Chip Select (WCS) input enables/disables Write Operations

• Read Chip Select (RCS) synchronous to RCLK

• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of four preselected offsets

• Dedicated serial clock input for serial programming of flag offsets

• User selectable input and output port bus sizing

-x20 in to x20 out

-x20 in to x10 out

-x10 in to x20 out

-x10 in to x10 out

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Empty and Full flags signal FIFO status

• Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into High-Impedance state

• JTAG port, provided for Boundary Scan function

• 208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch

• Easily expandable in depth and width

• Independent Read and Write Clocks (permit reading and writing simultaneously)

• High-performance submicron CMOS technology

• Industrial temperature range (-40°C to +85°C) is available

供应商 型号 品牌 批号 封装 库存 备注 价格
IDT
21+
240PBGA
13880
公司只售原装,支持实单
询价
IDT
23+
240BGA
9526
询价
IDT
23+
240PBGA
9000
原装正品,支持实单
询价
IDT
22+
240PBGA
9000
原厂渠道,现货配单
询价
IDT
1922+
BGA
8200
莱克讯原厂货源每一片都来自原厂原装现货薄利多
询价
IDT
23+
NA
19960
只做进口原装,终端工厂免费送样
询价