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H5AN8G4NAFR中文资料PDF规格书
H5AN8G4NAFR规格书详情
Description
The H5AN8G4NAFR-xxC, H5AN8G8NAFR-xxC and H5AN8G6NAFR-xxC are a 8Gb CMOS Double Data Rate
IV (DDR4) Synchronous DRAM, ideally suited for the main memory applications which requires large memory
density and high bandwidth. SK hynix 8Gb DDR4 SDRAMs offer fully synchronous operations referenced
to both rising and falling edges of the clock. While all addresses and control inputs are latched on
the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are
sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched
to achieve very high bandwidth.
FEATURES
• VDD=VDDQ=1.2V +/- 0.06V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• Programmable CAS latency 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19 and 20 supported
• Programmable additive latency 0, CL-1, and CL-2
supported (x4/x8 only)
• Programmable CAS Write latency (CWL) = 9, 10, 11,
12, 14, 16, 18
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 16banks
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
- 7.8 μs at 0oC ~ 85 oC
- 3.9 μs at 85oC ~ 95 oC
• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16)
• Driver strength selected by MRS
• Dynamic On Die Termination supported
• Two Termination States such as RTT_PARK and
RTT_NOM switchable by ODT pin
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
• This product in compliance with the RoHS directive.
• Internal Vref DQ level generation is available
• Write CRC is supported at all speed grades
• Maximum Power Saving Mode is supported
• TCAR(Temperature Controlled Auto Refresh) mode is
supported
• LP ASR(Low Power Auto Self Refresh) mode is supported
• Fine Granularity Refresh is supported
• Per DRAM Addressability is supported
• Geardown Mode(1/2 rate, 1/4 rate) is supported
• Programable Preamble for read and write is supported
• Self Refresh Abort is supported
• CA parity (Command/Address Parity) mode is supported
• Bank Grouping is applied, and CAS to CAS latency
(tCCD_L, tCCD_S) for the banks in the same or different
bank group accesses are available
• DBI(Data Bus Inversion) is supported(x8)
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
SKHYNIX |
22+ |
BGA |
50000 |
只做原装正品,假一罚十,欢迎咨询 |
询价 | ||
Hynix |
1844+ |
FBGA |
6528 |
只做原装正品假一赔十为客户做到零风险!! |
询价 | ||
SKHYNIX |
FBGA |
28942 |
原盒原标,正品现货 诚信经营 价格美丽 假一罚十 |
询价 | |||
SKHYNIX |
24+ |
ROHS |
990000 |
明嘉莱只做原装正品现货 |
询价 | ||
SKHYNIX |
23+ |
BGA |
90000 |
只做原厂渠道价格优势可提供技术支持 |
询价 | ||
SKHYNIX |
23+ |
BGA |
12700 |
优势原装现货假一赔十 |
询价 | ||
SKHYNIX |
19+ |
BGA |
30000 |
进口原装现货 |
询价 | ||
SKHYNIX |
19+ |
FBGA |
72564 |
原厂代理渠道,每一颗芯片都可追溯原厂; |
询价 | ||
SKHYNIX |
23+ |
BGA |
20000 |
原装正品保障-原包原盒可含税-深港可交货 |
询价 | ||
SKHYNIX/海力士 |
BGA |
12000 |
原装现货,长期供应,终端账期支持 |
询价 |