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EPM7064AELI44-7N中文资料PDF规格书
EPM7064AELI44-7N规格书详情
General Description
MAX 7000A (including MAX 7000AE) devices are high-density, high-performance devices based on Altera’s second-generation MAX architecture.
Features...
■ High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX®) architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
– MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
– EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
■ Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
■ Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
■ Enhanced ISP features
– Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
– ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
■ Pin-compatible with the popular 5.0-V MAX 7000S devices
■ High-density PLDs ranging from 600 to 10,000 usable gates
■ Extended temperature range
■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space
saving FineLine BGATM, and plastic J-lead chip carrier (PLCC)
packages
■ Supports hot-socketing in MAX 7000AE devices
■ Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
■ PCI-compatible
■ Bus-friendly architecture, including programmable slew-rate control
■ Open-drain output option
■ Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
■ Programmable power-up states for macrocell registers in
MAX 7000AE devices
■ Programmable power-saving mode for 50 or greater power
reduction in each macrocell
■ Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
■ Programmable security bit for protection of proprietary designs
■ 6 to 10 pin- or logic-driven output enable signals
■ Two global clock signals with optional inversion
■ Enhanced interconnect resources for improved routability
■ Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
■ Programmable output slew-rate control
■ Programmable ground pins
产品属性
- 型号:
EPM7064AELI44-7N
- 功能描述:
CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 36 IOs
- RoHS:
否
- 制造商:
Lattice
- 存储类型:
EEPROM
- 大电池数量:
128
- 最大工作频率:
333 MHz
- 延迟时间:
2.7 ns
- 可编程输入/输出端数量:
64
- 工作电源电压:
3.3 V
- 最大工作温度:
+ 90 C
- 最小工作温度:
0 C
- 封装/箱体:
TQFP-100
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
ALTERA |
20+ |
PLCC44 |
19570 |
原装优势主营型号-可开原型号增税票 |
询价 | ||
Altera |
19+ |
44-PLCC(16.59x16.59) |
56800 |
只卖原装正品!价格超越代理!可开增值税发票! |
询价 | ||
ALTERA |
22+ |
PLCC-44 |
2000 |
进口原装!现货库存 |
询价 | ||
ALTERA |
23+ |
132 |
询价 | ||||
ALTERA(阿尔特拉) |
22+ |
NA |
4000 |
原厂原装现货 |
询价 | ||
ALTERA |
22+ |
PLC |
32350 |
原装正品 假一罚十 公司现货 |
询价 | ||
ALTERA |
23+ |
PLCC44 |
30280 |
##公司主营品牌长期供应100%原装现货可含税提供技术 |
询价 | ||
ALTERA |
1013 |
PLC |
100 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
询价 | ||
ALTERA/阿尔特拉 |
23+ |
PLCC44 |
13500 |
代理授权直销,原装现货,假一罚十,长期稳定供应,特 |
询价 | ||
ALTERA/阿尔特拉 |
21+ |
PLCC44 |
3000 |
百域芯优势 实单必成 可开13点增值税发票 |
询价 |