The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to it.

Features

• 36MHz, general purpose PLL

• 4FSC based timing (use the EL4585 for 8FSC)

• Compatible with EL4583 sync separator

• VCXO, Xtal, or LC tank oscillator

• < 2ns jitter (VCXO)

• User controlled PLL capture and lock

• Compatible with NTSC and PAL TV formats

• 8 pre-programmed TV scan rate clock divisors

• Selectable external divide for custom ratios

• Single 5V, low current operation

• Pb-Free available (RoHS compliant)

Applications

• Pixel clock regeneration

• Video compression engine (MPEG) clock generator

• Video capture or digitization

• PIP (Picture-in-Picture) timing generator

• Text or graphics overlay timing

EL4584属于集成电路（IC） > 时钟发生器，PLL，频率合成器。瑞萨科技有限公司制造生产的EL4584时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。