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CY7C2565XV18-600BZC中文资料PDF规格书
厂商型号 |
CY7C2565XV18-600BZC |
参数属性 | CY7C2565XV18-600BZC 封装/外壳为165-LBGA;包装为托盘;类别为集成电路(IC) > 存储器;产品描述:IC SRAM 72MBIT PARALLEL 165FBGA |
功能描述 | 72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
文件大小 |
614.89 Kbytes |
页面数量 |
29 页 |
生产厂商 | CypressSemiconductor |
企业简称 |
Cypress【赛普拉斯】 |
中文名称 | 赛普拉斯半导体公司官网 |
原厂标识 | |
数据手册 | |
更新时间 | 2024-6-4 18:03:00 |
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CY7C2565XV18-600BZC规格书详情
Functional Description
The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 633 MHz clock for high bandwidth
■ Four-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-die termination (ODT) feature
❐ Supported for D[x:0], BWS[x:0], and K/K inputs
■ Single multiplexed address input bus latches address inputs for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR® II+ Xtreme operates with 2.5 cycle read latency when DOFF is asserted HIGH
■ Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted LOW
■ Available in × 18, and × 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to 1.6 V
❐ Supports 1.5 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase-locked loop (PLL) for accurate data placement
产品属性
- 产品编号:
CY7C2565XV18-600BZC
- 制造商:
Cypress Semiconductor Corp
- 类别:
集成电路(IC) > 存储器
- 包装:
托盘
- 存储器类型:
易失
- 存储器格式:
SRAM
- 技术:
SRAM - 同步,QDR II+
- 存储容量:
72Mb(2M x 36)
- 存储器接口:
并联
- 电压 - 供电:
1.7V ~ 1.9V
- 工作温度:
0°C ~ 70°C(TA)
- 安装类型:
表面贴装型
- 封装/外壳:
165-LBGA
- 供应商器件封装:
165-FBGA(13x15)
- 描述:
IC SRAM 72MBIT PARALLEL 165FBGA
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
SPANSION(飞索) |
2021+ |
FBGA-165(13x15) |
499 |
询价 | |||
Cypress |
21+ |
165FBGA (13x15) |
13880 |
公司只售原装,支持实单 |
询价 | ||
Cypress |
23+ |
165FBGA (13x15) |
9000 |
原装正品,支持实单 |
询价 | ||
CYPRESS/赛普拉斯 |
23+ |
NA |
25630 |
原装正品 |
询价 | ||
CYPRESS/赛普拉斯 |
22+ |
N/A |
12245 |
现货,原厂原装假一罚十! |
询价 | ||
CYPRESS/赛普拉斯 |
标准封装 |
58877 |
一级代理原装正品现货期货均可订购 |
询价 | |||
CYPRESS/赛普拉斯 |
22+ |
NA |
10000 |
绝对全新原装现货热卖 |
询价 | ||
Cypress |
22+/23+ |
165-FBGA(13x15) |
9800 |
原装进口公司现货假一赔百 |
询价 | ||
CYPRESS/赛普拉斯 |
21+ |
NA |
12820 |
只做原装,质量保证 |
询价 | ||
Cypress |
21+ |
25000 |
原厂原包 深圳现货 主打品牌 假一赔百 可开票! |
询价 |