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CY7C1618KV18-300BZXC中文资料PDF规格书
厂商型号 |
CY7C1618KV18-300BZXC |
参数属性 | CY7C1618KV18-300BZXC 封装/外壳为165-LBGA;包装为卷带(TR);类别为集成电路(IC) > 存储器;产品描述:IC SRAM 144MBIT PARALLEL 165FBGA |
功能描述 | 144-Mbit DDR II SRAM Two-Word Burst Architecture |
文件大小 |
753 Kbytes |
页面数量 |
32 页 |
生产厂商 | CypressSemiconductor |
企业简称 |
Cypress【赛普拉斯】 |
中文名称 | 赛普拉斯半导体公司官网 |
原厂标识 | |
数据手册 | |
更新时间 | 2024-6-14 22:59:00 |
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CY7C1618KV18-300BZXC规格书详情
Functional Description
The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. On CY7C1618KV18 and CY7C1620KV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1618KV18 and two 36-bit words in the case of CY7C1620KV18 sequentially into or out of the device.
Features
■ 144-Mbit density (8M × 18, 4M × 36)
■ 333 MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5-cycle read latency when DOFF is asserted high
■ Operates similar to DDR I device with one cycle read latency when DOFF is asserted low
■ 1.8-V core power supply with high-speed transceiver logic (HSTL) inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V–VDD)
❐ Supports both 1.5-V and 1.8-V I/O supply
■ Available in 165-ball fine-pitch ball grid array (FBGA) package (15 × 17 × 1.4 mm)
■ Offered in Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
产品属性
- 产品编号:
CY7C1618KV18-300BZXC
- 制造商:
Cypress Semiconductor Corp
- 类别:
集成电路(IC) > 存储器
- 包装:
卷带(TR)
- 存储器类型:
易失
- 存储器格式:
SRAM
- 技术:
SRAM - 同步,QDR II
- 存储容量:
144Mb(4M x 36)
- 存储器接口:
并联
- 电压 - 供电:
1.7V ~ 1.9V
- 工作温度:
0°C ~ 70°C(TA)
- 安装类型:
表面贴装型
- 封装/外壳:
165-LBGA
- 供应商器件封装:
165-FBGA(15x17)
- 描述:
IC SRAM 144MBIT PARALLEL 165FBGA
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
CYPRESS(赛普拉斯) |
23+ |
LBGA165 |
7350 |
现货供应,当天可交货!免费送样,原厂技术支持!!! |
询价 | ||
CYPRESS/赛普拉斯 |
23+ |
NA/ |
46 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
询价 | ||
CYPRESS |
2016+ |
FBGA165 |
3526 |
假一罚十进口原装现货原盘原标! |
询价 | ||
CYPRESS |
23+ |
NA |
1221 |
专业电子元器件供应链正迈科技特价代理QQ1304306553 |
询价 | ||
Cypress |
22+ |
NA |
77 |
加我QQ或微信咨询更多详细信息, |
询价 | ||
SPANSION(飞索) |
2021+ |
FBGA-165(15x17) |
499 |
询价 | |||
22+ |
5000 |
询价 | |||||
CYPRESS/赛普拉斯 |
22+ |
BGA |
20000 |
原装现货,实单支持 |
询价 | ||
CYPRESS/赛普拉斯 |
2022 |
FBGA165 |
80000 |
原装现货,OEM渠道,欢迎咨询 |
询价 | ||
Cypress |
165-FBGA |
5800 |
Cypress一级分销,原装原盒原包装! |
询价 |