CIRCUIT DESCRIPTION

The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference clock (REF CLK).

The setup uses the AD9520 as the REF CLK source for each AD9910 DDS. The AD9520 runs off an external crystal and the internal PLL. The AD9520 distributes phase aligned 1 GHz REF CLKs (PECL outputs) to all four AD9910 evaluation boards. It also provides a CMOS output clock to the Tektronix DG2020A data pattern generator for the IO_UPDATE.

CIRCUIT FUNCTION AND BENEFITS

Synchronization of multiple DDS devices allows precise digital tuning control of the phase and amplitude across multiple frequency carriers. This type of control is useful in radar applications and quadrature (I/Q) upconversion for side-band suppression.

The circuit in Figure 1 demonstrates how to synchronize four AD9910 1 GSPS, DDS chips using the AD9520 clock generator and the ADCLK846 clock fanout buffer. The result is precise phase alignment between the clock and output signals of four AD9910 devices.

AD9910属于集成电路（IC） > 直接数字合成（DDS）。亚德诺半导体技术有限公司制造生产的AD9910直接数字合成（DDS）直接数字合成 (DDS) 用于由数字信号生成不同频率的模拟波形。在必须大范围扫描的无线系统中可用于频率控制。主时钟频率有 5MHz、16MHz、16.776MHz、25MHz、50MHz、75MHz、125MHz、180MHz、200MHz、250MHz、300MHz、400MHz、500MHz、1GHz、2.5GHz 和 3GHz，分辨率为 10 b、12 b 或 14 b。