General Description:

The 9DB633 zero-delay buffer supports PCIe Gen3

requirements, while being backwards compatible to PCIe

Gen2 and Gen1. The 9DB633 is driven by a differential SRC

output pair from an IDT 932S421 or 932SQ420 or equivalent

main clock generator. It attenuates jitter on the input clock

and has a selectable PLL bandwidth to maximize

performance in systems with or without Spread-Spectrum

clocking. An SMBus interface allows control of the PLL

bandwidth and bypass options, while 2 clock request (OE#)

pins make the 9DB633 suitable for Express Card

applications.

Features/Benefits:

• OE# pins/Suitable for Express Card applications

• PLL or bypass mode/PLL can dejitter incoming clock

• Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL's

• Spread Spectrum Compatible/tracks spreading input

clock for low EMI

• SMBus Interface/unused outputs can be disabled

9DB633属于集成电路（IC） > 应用特定时钟/定时。瑞萨科技有限公司制造生产的9DB633应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。