1. General description

The 74LVT02 is a quad 2-input NOR gate. This device is fully specified for partial power down

applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging

backflow current through the device when it is powered down.

2. Features and benefits

• Wide supply voltage range from 2.7 V to 3.6 V

• Output capability: +64 mA and -32 mA

• Direct interface with TTL levels

• Overvoltage tolerant inputs to 5.5 V

• Power-up 3-state

• No bus current loading when output is tied to 5 V bus

• IOFF circuitry provides partial Power-down mode operation

• Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• ESD protection:

• HBM JESD22-A114E exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to 85 °C

74LVT02PW属于集成电路（IC） > 门和反相器。安世半导体(中国)有限公司制造生产的74LVT02PW门和反相器逻辑栅极和逆变器系列中的产品对单个逻辑信号执行基本逻辑运算（例如 AND、NOT、OR 等）。与触发器不同，它们不能够存储信息，不会对提供给其输入的信号立即做出响应。虽然早就被集成电路实施形式所取代，以用于实现复杂功能，但分立栅极仍可在仅需要非常简单逻辑功能的情况下使用。