General description

The 74LVC244A; 74LVCH244A is an octal non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times.

Inputs can be driven from either 3.3 V or 5.0 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 V and 5 V environment.

The 74LVCH244A bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

Features and benefits

■ 5 V tolerant inputs/outputs for interfacing with 5 V logic

■ Wide supply voltage range from 1.2 V to 3.6 V

■ CMOS low-power consumption

■ Direct interface with TTL levels

■ Inputs accept voltages up to 5.5 V

■ High-impedance when VCC = 0 V

■ Bus hold on all data inputs (74LVCH244A only)

■ Complies with JEDEC standard:

◆ JESD8-7A (1.65 V to 1.95 V)

◆ JESD8-5A (2.3 V to 2.7 V)

◆ JESD8-C/JESD36 (2.7 V to 3.6 V)

■ ESD protection:

◆ HBM JESD22-A114F exceeds 2000 V

◆ MM JESD22-A115B exceeds 200 V

◆ CDM JESD22-C101E exceeds 1000 V

■ Specified from -40 °C to +85 °C and -40 °C to +125 °C

74LVCH244APW属于集成电路（IC） > 缓冲器，驱动器，接收器，收发器。恩智浦半导体公司制造生产的74LVCH244APW缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。