1. General description

The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE),

master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops

stores the state of their individual D-inputs that meet the set-up and hold times requirements on the

LOW to HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their

data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip-flops

are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance

OFF-state. Operation of the OE input does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied

to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V

applications.

2. Features and benefits

• 5 V tolerant inputs/outputs for interfacing with 5 V logic

• Wide supply voltage range from 1.2 V to 3.6 V

• CMOS low power consumption

• Direct interface with TTL levels

• Flow-through pinout architecture

• 9-bit positive edge-triggered register

• Independent register and 3-state buffer operation

• Complies with JEDEC standard:

• JESD8-7A (1.65 V to 1.95 V)

• JESD8-5A (2.3 V to 2.7 V)

• JESD8-C/JESD36 (2.7 V to 3.6 V)

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-B exceeds 200 V

• CDM JESD22-C101E exceeds 1000 V

• Specified from -40 °C to +85 °C and -40 °C to +125 °C.

74LVC823APW属于集成电路（IC） > 触发器。安世半导体(中国)有限公司制造生产的74LVC823APW触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。