1. General description

The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP)

inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock

input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition

of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock

transition, for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall

times.

2. Features and benefits

• 5 V tolerant inputs for interlacing with 5 V logic

• Wide supply voltage range from 1.2 V to 3.6 V

• CMOS low power consumption

• Direct interface with TTL levels

• Complies with JEDEC standard:

• JESD8-7A (1.65 V to 1.95 V)

• JESD8-5A (2.3 V to 2.7 V)

• JESD8-C/JESD36 (2.7 V to 3.6 V)

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-B exceeds 200 V

• CDM JESD22-C101E exceeds 1000 V

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

74LVC74APW属于集成电路（IC） > 触发器。安世半导体(中国)有限公司制造生产的74LVC74APW触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。