1. General description

The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock

(CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that

meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in

the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This

feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

• Wide supply voltage range from 1.65 V to 5.5 V

• Overvoltage tolerant inputs to 5.5 V

• High noise immunity

• ±24 mA output drive (VCC = 3.0 V)

• CMOS low power consumption

• Direct interface with TTL levels

• IOFF circuitry provides partial Power-down mode operation

• Latch-up performance exceeds 250 mA

• Complies with JEDEC standard:

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8-B/JESD36 (2.7 V to 3.6 V)

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

74LVC1G74GN属于集成电路（IC） > 触发器。安世半导体(中国)有限公司制造生产的74LVC1G74GN触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。