1. General description

The 74LV540A is an 8-bit inverting buffer/line driver with 3-state outputs. The device

features two output enables (OE1 and OE2). A HIGH on OEn causes the associated

outputs to assume a high-impedance OFF-state.

Inputs are overvoltage tolerant. This feature allows the use of these devices as translators

in mixed voltage environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall

times.

This device is fully specified for partial power down applications using IOFF. The IOFF

circuitry disables the output, preventing the potentially damaging backflow current through

the device when it is powered down.

2. Features and benefits

 Wide supply voltage range from 2.0 V to 5.5 V

 Maximum tpd of 6 ns at 5 V

 Typical VOL(p) < 0.8 V at VCC = 3.3 V, Tamb = 25 C

 Typical VOH(v) > 2.3 V at VCC = 3.3 V, Tamb = 25 C

 Supports mixed-mode voltage operation on all ports

 IOFF circuitry provides partial Power-down mode operation

 Latch-up performance exceeds 250 mA per JESD 78 Class II

 ESD protection:

 HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 3 kV

 MM JESD22-A115-A exceeds 150 V

 CDM JESD22-C101E exceeds 2 kV

 Specified from 40 C to +85 C and from 40 C to +125 C

74LV540APW属于集成电路（IC） > 缓冲器，驱动器，接收器，收发器。安世半导体(中国)有限公司制造生产的74LV540APW缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。