1. General description

The 74HC374; 74HCT374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs.

The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state

of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH

clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state.

Operation of the OE input does not affect the state of the flip-flops. Inputs also include clamp

diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of

VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Input levels:

• For 74HC374: CMOS level

• For 74HCT374: TTL level

• Octal bus interface

• Non-inverting 3-state outputs

• 8-bit positive, edge-triggered register

• Common 3-state output enable input

• Independent register and 3-state buffer operation

• Complies with JEDEC standards

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

74HC374PW属于集成电路（IC） > 触发器。安世半导体(中国)有限公司制造生产的74HC374PW触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。