1. General description

The 74AVC16245 is a 16-bit transceiver featuring non-inverting 3-state bus compatible

outputs in both send and receive directions. The device features two output enable inputs

(nOE) for easy cascading and two send/receive inputs (nDIR) for direction control.

Inputs nOE control the outputs so that the buses are effectively isolated. This device can

be used as two 8-bit transceivers or one 16-bit transceiver.

The 74AVC16245 is designed to have an extremely fast propagation delay and a

minimum amount of power consumption.

To ensure the high-impedance output state during power-up or power-down, tie pins nOE

to VCC through a pull-up resistor (Live Insertion).

A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line

drive during transient (see Figure 4 and Figure 5)

2. Features and benefits

 Wide supply voltage range from 1.2 V to 3.6 V

 Complies with JEDEC standards:

 JESD8-7 (1.2 V to 1.95 V)

 JESD8-5 (1.8 V to 2.7 V)

 JESD8-1A (2.7 V to 3.6 V)

 CMOS low power consumption

 Input/output tolerant up to 3.6 V

 Dynamic Controlled Output (DCO) circuit dynamically changes output impedance,

resulting in noise reduction without speed degradation

 Low inductance multiple VCC and GND pins to minimize noise and ground bounce

 Supports Live Insertion

74AVC16245DGG属于集成电路（IC） > 缓冲器，驱动器，接收器，收发器。安世半导体(中国)有限公司制造生产的74AVC16245DGG缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。