1. General description

The 74AUP1T34 is a single dual supply translating buffer. Input A is referenced to VCC(A) and

output Y is referenced to VCC(Y). Schmitt-trigger action at all inputs makes the circuit tolerant

of slower input rise and fall times. This device ensures very low static and dynamic power

consumption across the entire VCC range from 1.1 V to 3.6 V. This device is fully specified for

partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the

potentially damaging backflow current through the device when it is powered down.

2. Features and benefits

• Wide supply voltage range from 1.1 V to 3.6 V

• CMOS low power dissipation

• High noise immunity

• Complies with JEDEC standards:

• JESD8-7 (1.2 V to 1.95 V)

• JESD8-5 (1.8 V to 2.7 V)

• JESD8-B (2.7 V to 3.6 V)

• ESD protection:

• HBM JESD22-A114F Class 3A exceeds 5000 V

• MM JESD22-A115-A exceeds 200 V

• CDM JESD22-C101E exceeds 1000 V

• Wide supply voltage range:

• VCC(A): 1.1 V to 3.6 V

• VCC(Y): 1.1 V to 3.6 V

• Low static power consumption; ICC = 0.9 μA (maximum)

• Each port operates over the full 1.1 V to 3.6 V power supply range

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Overvoltage tolerant inputs to 3.6 V

• Low noise overshoot and undershoot < 10 of VCC

• IOFF circuitry provides partial Power-down mode operation

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1T34属于集成电路（IC） > 转换器，电平移位器。安世半导体(中国)有限公司制造生产的74AUP1T34转换器，电平移位器逻辑转换器或电平移位器 IC 可用于在数字逻辑设备之间传递信息，这些设备可在不同/不兼容的供电电压下工作，或可实现不同的信令方式。例如，可以将需要 5 V 电源的数字输出传感器连接到具有 3.3 V I/O 电源的 FPGA，或者在 CMOS 或 TTL 等单端信令方式与 PECL 或 LVDS 等差分技术之间进行转换。