1. General description

The 74AUP1G97 is a configurable multiple function gate with Schmitt-trigger inputs. The device

can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter

and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. This device

ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to

3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

• Wide supply voltage range from 0.8 V to 3.6 V

• CMOS low power dissipation

• High noise immunity

• ESD protection:

• HBM JESD22-A114F exceeds 5000 V

• MM JESD22-A115-A exceeds 200 V

• CDM JESD22-C101E exceeds 1000 V

• Complies with JEDEC standards:

• JESD8-12 (0.8 V to 1.3 V)

• JESD8-11 (0.9 V to 1.65 V)

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• Low static power consumption; ICC = 0.9 μA (maximum)

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Overvoltage tolerant inputs to 3.6 V

• Low noise overshoot and undershoot < 10 of VCC

• IOFF circuitry provides partial Power-down mode operation

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G97属于集成电路（IC） > 门和反相器 - 多功能，可配置。安世半导体(中国)有限公司制造生产的74AUP1G97门和反相器 - 多功能，可配置可配置逻辑栅极系列产品能以与标准逻辑栅极类似的方式，对单个逻辑信号执行基本逻辑运算，但并非局限于一个特定功能（例如 AND、NAND 等）。它们通常在内部使用少量逻辑门来实现，经过选择和互连后，以便通过选择操作数据所应用的输入以及任何未使用的输入在驱动后的逻辑状态，来配置所实现的整体逻辑功能。