1. General description

The 74AUP1G240 is a 1-bit inverting buffer/line driver with 3-state outputs. The device features

an output enable (OE). A HIGH on OE causes the output to assume a high-impedance OFF-state.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This

device ensures very low static and dynamic power consumption across the entire VCC range from

0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The

IOFF circuitry disables the output, preventing the potentially damaging backflow current through the

device when it is powered down.

2. Features and benefits

• Wide supply voltage range from 0.8 V to 3.6 V

• High noise immunity

• Complies with JEDEC standards:

• JESD8-12 (0.8 V to 1.3 V)

• JESD8-11 (0.9 V to 1.65 V)

• JESD8-7 (1.2 V to 1.95 V)

• JESD8-5 (1.8 V to 2.7 V)

• JESD8-B (2.7 V to 3.6 V)

• ESD protection:

• HBM JESD22-A114F exceeds 5000 V

• MM JESD22-A115-A exceeds 200 V

• CDM JESD22-C101E exceeds 1000 V

• Low static power consumption; ICC = 0.9 μA (maximum)

• Latch-up performance exceeds 100 mA per JESD 78 Class II

• Overvoltage tolerant inputs to 3.6 V

• Low noise overshoot and undershoot < 10 of VCC

• Input-disable feature allows floating input conditions

• IOFF circuitry provides partial Power-down mode operation

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G240属于集成电路（IC） > 缓冲器，驱动器，接收器，收发器。安世半导体(中国)有限公司制造生产的74AUP1G240缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。