1 General description

The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting

registered transceiver. Two 8-bit back to back registers store data flowing in both

directions between two bidirectional buses. Data applied to the inputs is entered and

stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock

enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but

is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow

from A inputs to B outputs is the same as for B inputs to A outputs.

2 Features and benefits

• CMOS low-power consumption

• Multibyte flow-through pinout architecture

• Low inductance, multiple center power and ground pins for minimum noise and ground

bounce

• Direct interface with TTL levels

• Output drive capability 50 Ω transmission lines at 85 °C

• Complies with JEDEC standard JESD8-B

74ALVCH16952DGG属于集成电路（IC） > 缓冲器，驱动器，接收器，收发器。安世半导体(中国)有限公司制造生产的74ALVCH16952DGG缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。