1 General description

The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs

for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold

data inputs which eliminate the need for external pull-up resistors to hold unused inputs.

The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock

(nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clockenable

(nCE) input are provided for each total 9-bit section.

With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of

their individual nDn-inputs that meet the set-up and hold time requirements on the

LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching

the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go

LOW independently of the clock.

When nOE is LOW, the contents of the flip-flops are available at the outputs. When the

nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE

input does not affect the state of flip-flops.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic

level.

2 Features and benefits

• Wide supply voltage range from 1.2 V to 3.6 V

• CMOS low-power consumption

• Direct interface with TTL levels

• Current drive ± 24 mA at 3.0 V

• MULTIBYTE flow-through standard pin-out architecture

• Low inductance multiple VCC and GND pins for minimum noise and ground bounce

• Output drive capability 50 Ω transmission lines at 85°C

• All data inputs have bushold

• Complies with JEDEC standard no. 8-1A

• Complies with JEDEC standards:

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V)

• ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

– CDM JESD22-C101E exceeds 1000 V

74ALVCH16823DGG属于集成电路（IC） > 触发器。安世半导体(中国)有限公司制造生产的74ALVCH16823DGG触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。