1. General description

The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, Dtype

flip-flops and control circuitry arranged for multiplexed transmission of data directly from the

data bus or from the internal storage registers.

Data on the ‘A’ or ‘B’, or both buses, will be stored in the internal registers, at the appropriate clock

inputs (nCPAB or nCPBA) regardless of the select inputs (nSAB and nSBA) or output enable

(nOEAB and nOEBA) control inputs.

Depending on the select inputs nSAB and nSBA data can directly go from input to output (real-time

mode) or data can be controlled by the clock (storage mode), when OE inputs permit this operating

mode.

The output enable inputs nOEAB and nOEBA determine the operation mode of the transceiver.

When nOEAB is LOW, no data transmission from nBn to nAn is possible and when nOEBA is

HIGH, no data transmission from nBn to nAn is possible.

When nSAB and nSBA are in the real-time transfer mode, it is also possible to store data without

using the internal D-type flip-flops by simultaneously enabling nOEAB and nOEBA. In this

configuration each output reinforces its input.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

2. Features and benefits

• Wide supply voltage range of 1.2 V to 3.6 V

• CMOS low power consumption

• Direct interface with TTL levels

• Current drive ±24 mA at VCC = 3.0 V.

• MULTIBYTE flow-through standard pin-out architecture

• Low inductance multiple VCC and GND pins for minimum noise and ground bounce

• All data inputs have bushold

• Output drive capability 50 Ω transmission lines at 85 °C

• Complies with JEDEC standards:

• JESD8-5 (2.3 V to 2.7 V)

• JESD8B/JESD36 (2.7 V to 3.6 V)

• ESD protection:

• HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

• CDM JESD22-C101E exceeds 1000 V

74ALVCH16652DGG属于集成电路（IC） > 缓冲器，驱动器，接收器，收发器。安世半导体(中国)有限公司制造生产的74ALVCH16652DGG缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。