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72V36110L7-5PFG中文资料PDF规格书
厂商型号 |
72V36110L7-5PFG |
参数属性 | 72V36110L7-5PFG 封装/外壳为128-LQFP;包装为管件;类别为集成电路(IC) > FIFO 存储器;产品描述:IC MEM FIFO 131KX36 128QFP |
功能描述 | 3.3 VOLT HIGH-DENSITY SUPERSYNC II |
文件大小 |
310.35 Kbytes |
页面数量 |
48 页 |
生产厂商 | Integrated Device Technology, Inc. |
企业简称 |
IDT【集成器】 |
中文名称 | 深圳市集成器件技术有限公司官网 |
原厂标识 | |
数据手册 | |
更新时间 | 2024-5-21 18:30:00 |
72V36110L7-5PFG规格书详情
DESCRIPTION:
The IDT72V36100/72V36110 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is
written to an empty FIFO to the time it can be read, is fixed and short.
• Asynchronous/Synchronous translation on the read or write ports
• High density offerings up to 4 Mbit
FEATURES:
• Choose among the following memory organizations:
IDT72V36100 - 65,536 x 36
IDT72V36110 - 131,072 x 36
• Higher density, 2Meg and 4Meg SuperSync II FIFOs
• Up to 166 MHz Operation of the Clocks
• User selectable Asynchronous read and/or write ports (PBGA Only)
• User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• 5V input tolerant
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost
Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• JTAG port, provided for Boundary Scan function (PBGA Only)
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic
Ball Grid Array (PBGA) (with additional features)
• Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/
72V3670/72V3680/72V3690) family
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
产品属性
- 产品编号:
72V36110L7-5PFGI8
- 制造商:
Renesas Electronics America Inc
- 类别:
集成电路(IC) > FIFO 存储器
- 系列:
72V
- 包装:
管件
- 存储容量:
4.7M(131K x 36)
- 功能:
同步
- 数据速率:
133.3MHz
- 访问时间:
5ns
- 电流 - 供电(最大值):
40mA
- 总线方向:
单向
- 扩充类型:
深度,宽度
- 可编程标志支持:
是
- 中继能力:
是
- FWFT 支持:
是
- 工作温度:
-40°C ~ 85°C
- 安装类型:
表面贴装型
- 封装/外壳:
128-LQFP
- 供应商器件封装:
128-TQFP(14x20)
- 描述:
IC MEM FIFO 131KX36 128QFP
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
RENESAS(瑞萨)/IDT |
23+ |
TQFP128(14x20) |
6000 |
询价 | |||
RENESAS(瑞萨)/IDT |
23+ |
TQFP128(14x20) |
7350 |
现货供应,当天可交货!免费送样,原厂技术支持!!! |
询价 | ||
Renesas |
23+ |
128-LQFP |
889 |
确保原装正品,一站式配单-认准水星电子。 |
询价 | ||
IDT |
06+07+ |
LQFP |
13 |
询价 | |||
RENESAS(瑞萨)/IDT |
2021+ |
TQFP-128(14x20) |
499 |
询价 | |||
RENESAS(瑞萨电子) |
22+ |
NA |
500000 |
万三科技,秉承原装,购芯无忧 |
询价 | ||
RENESAS(瑞萨)/IDT |
2022+原装正品 |
TQFP-128(14x20) |
18000 |
支持工厂BOM表配单 公司只做原装正品货 |
询价 | ||
Renesas Electronics America In |
24+ |
128-LQFP |
9350 |
独立分销商,公司只做原装,诚心经营,免费试样正品保证 |
询价 | ||
RENESAS(瑞萨)/IDT |
2117+ |
TQFP-128(14x20) |
315000 |
36个/托盘一级代理专营品牌!原装正品,优势现货,长 |
询价 | ||
IDT, Integrated Device Technol |
21+ |
128-TQFP(14x20) |
53200 |
一级代理/放心采购 |
询价 |