FEATURES:

• Choose among the following memory organizations:

72V36100 ⎯ 65,536 x 36

72V36110 ⎯ 131,072 x 36

• Higher density, 2Meg and 4Meg SuperSync II FIFOs

• Up to 166 MHz Operation of the Clocks

• User selectable Asynchronous read and/or write ports (CABGA Only)

• User selectable input and output port bus-sizing

- x36 in to x36 out

- x36 in to x18 out

- x36 in to x9 out

- x18 in to x36 out

- x9 in to x36 out

• Big-Endian/Little-Endian user selectable byte representation

• 5V input tolerant

• Fixed, low first word latency

• Zero latency retransmit

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

• Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

• Program programmable flags by either serial or parallel means

• Select Standard timing (using EF and FF flags) or First Word Fall

Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• JTAG port, provided for Boundary Scan function (CABGA Only)

• Independent Read and Write Clocks (permit reading and writing

simultaneously)

• Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Chip

Array BGA (CABGA) (with additional features)

• Pin compatible to the SuperSync II (72V3640/72V3650/72V3660/

72V3670/72V3680/72V3690) family

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

72V36110L6BCY属于集成电路（IC） > FIFO 存储器。瑞萨科技有限公司制造生产的72V36110L6BCYFIFO 存储器先入先出 (FIFO) 存储器可用于数字信息的短期存储，其中信息检索顺序和序列与信息存储顺序和序列相同。这类产品又称为队列或缓冲存储器，通常用于在单独的设备之间交换信息，尤其是在数据以不同的速率或在略微不同的时间点生成和使用的情况下。