FEATURES:

• Guaranteed Low Skew < 25ps (max)

• Very low duty cycle distortion

• High speed propagation delay < 2.5ns. (max)

• Up to 250MHz operation

• Very low CMOS power levels

• 1.5V VDDQ for HSTL interface

• Hot insertable and over-voltage tolerant inputs

• 3-level inputs for selectable interface

• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input

interface

• Selectable differential or single-ended inputs and fi ve single-ended outputs

• 2.5V VDD

• Available in TSSOP package

• For new designs use functional replacement 8L30110

DESCRIPTION:

The 5T90533 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to fi ve single-ended outputs buffer

built on advanced metal CMOS technology. The SDR clock buffer fanout

from a single or differential input to fi ve single-ended outputs reduces the

loading on the preceding driver and provides an effi cient clock distribution

network. The 5T90533 can act as a translator from a differential HSTL,

eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL

input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is

controlled by 3-level input signals that may be hard-wired to appropriate

high-mid-low levels. Multiple power and grounds reduce noise

5T90533属于集成电路（IC） > 时钟缓冲器，驱动器。瑞萨科技有限公司制造生产的5T90533时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。